The present invention relates generally to direct memory access (DMA) operations in a computer system, and more particularly, to appending additional DMA commands to a DMA command chain without terminating the DMA operation.
Direct memory access (DMA) controllers are currently used to read graphics data, such as texture information, pixel information, and depth information, from system memory and write the graphics data to a graphics memory. The DMA controller operates according to DMA commands, which are normally processed in a pipeline fashion. That is, DMA commands are placed in a queue or command chain and sequentially executed by the DMA controller.
Typically, the last DMA command in the chain instructs the DMA controller to terminate the DMA operation. Additional DMA commands may be added to the chain of commands after the DMA controller has begun to sequentially execute the original commands. The chain is extended by removing the last command of the original chain of DMA commands, that is the command terminating the DMA operation, and appending new DMA commands. However, the appended commands must be added to the queue before the terminate command at the end of the original chain has been reached. Consequently, the processor must query the DMA controller to determine if the DMA operation has been terminated before additional DMA commands can be added to the queue.
One method that has been used to determine whether the DMA operation has been terminated is to have a system processor query the DMA controller to determine if the last DMA command in the command chain, namely, the terminate command, has been executed. Where the DMA operation has already terminated, no additional DMA commands can be appended to the chain, and a new DMA operation must be initiated by the system processor. A drawback to this method is that the system processor becomes idle as it polls the DMA controller, thus, wasting several clock cycles waiting for a response.
Another conventional method that has been used is for the DMA controller to send an interrupt to the system processor when the DMA command chain is completed. However, the interrupt sent by the DMA controller causes the system processor to perform a task switch. The system processor is forced to switch from a user mode to a kernel mode, and then back again. Both of these methods are relatively time consuming, and reduce the efficiency of the overall system.
The present invention relates to a direct memory access (DMA) controller for controlling memory access operations on a memory. The DMA controller executes DMA commands in a command chain during a memory access operation. The DMA commands are stored in a memory and have a respective address. The DMA controller can enter a self-linking mode where additional DMA commands can be appended to the end of the command chain without terminating the memory access operation, although the last DMA command of the command chain has been executed by the DMA controller. The DMA controller enters the self-linking mode when a link-address provided by the last DMA command matches a code. The code to cause the DMA controller to enter the self-linking mode may be the address of last executed DMA command, that is, a link address which points to itself. Alternatively, the code may also be a predetermined bit pattern. The DMA controller exits the self-linking command and continues the memory access operation upon detecting a new link address for a new DMA command that is to be appended to the command chain. The new link address may be detected by having the DMA controller periodically check the link address of the last executed DMA command.